In the field of semiconductor device manufacturing, there is a need for providing semiconductor devices such as complementary metal oxide semiconductor (CMOS) devices that contain ultra-sub-lithographic features. That is, there is a need for providing CMOS lines in which the dimensions thereof are less than 0.7 F, wherein F is the minimal lithographic dimension related to the wavelength of exposure.
In the prior art, CMOS devices that have a gate microstructure are fabricated using photolithography, which includes the steps of applying a photoresist and an optional antireflective coating (ARC) to a material needing patterning; exposing the photoresist to a pattern of radiation and developing the exposed photoresist; resist, antireflective coating (ARC), or hard mask trimming; and pattern transfer with or without trimming.
The prior art process is shown, for example, in FIGS. 1A–1D. In particular, FIG. 1A illustrates an intermediate structure after photolithography. The intermediate structure includes substrate 10, gate dielectric 12, gate conductor 14, hard mask 16 and a plurality of patterned photoresists labeled as 18a, 18b and 18c. Each patterned photoresist has a line width, L, associated therewith. In the example shown, L1 of patterned photoresist 18a is greater than Lnom of patterned photoresist 18b which is greater than L2 of patterned photoresist 18c. The Lnom denotes the actual line width of the patterned photoresist needed to achieve a desired lithographic feature; in the drawing the dotted region about L1 and L2 represents Lnom. As shown, the photolithographic processing step inherently introduces a variation in line width, i.e., variation of critical dimension CD, into the structure. The variation is typically from line to line within a circuit, chip, or wafer. The variation within a single line can also be significant. FIG. 1A schematically represents all types of line width variation.
After providing the patterned photoresists atop the gate structure, the pattern is transferred from the patterned photoresists into the hard mask 16 providing patterned hard masks 16a, 16b, and 16c. As is shown in FIG. 1B, the variation in critical dimension is still present in the structure after the first pattern transfer step.
To achieve microstructures having an ultra-sub-lithographic feature (about 0.7 F), the patterned hard masks 16a, 16, and 16c are typically trimmed by a conventional etching process such as an isotropic dry etch, e.g., a COR (chemical oxide removal) etch. Alternatively, an antireflective coating and/or resist itself can be trimmed during the hard mask etching step. Alternatively, the lines themselves can be trimmed during their etching. The later trimming process is often referred to as active trimming. Any combination of trimming processes leads to a sub-lithographic structure of final lines. For simplification of drawings, the trimming process is shown at the hard mask level. The structure formed after the patterned hard masks have been trimmed is shown, for example, in FIG. 1C. The patterned and trimmed hard masks are denoted as 16a′, 16b′ and 16c′. Note that the variation in critical dimension is still present in the structure after the patterned hard masks have been trimmed. Furthermore, the relative variation in CD with respect to the nominal or average CD increases with any known combination of trimming processes.
Following the trimming step, the pattern is transferred from the patterned and trimmed hard masks into the underlying gate conductor 14 using an etching process providing patterned gate conductors 14a, 14b, and 14c. After the second pattern transfer step, the patterned and trimmed hard masks are typically removed providing the structure shown, for example, in FIG. 1D. The prior art gate microstructure shown in FIG. 1D also has a variation in CD.
The variation in CD that results from this prior art process is typical about 30% (6 σ, where σ is a standard deviation parameter or range). FIG. 2 shows a typical distribution of the CD variation for the prior art gate microstructure shown in FIG. 1D. Such a high variation in CD is unwanted since it does not permit reliable fabrication of ultra-sub-lithographic features. Additionally, the high variation in CD is unwanted since it hinders device performance and manufacturing yield and results in a substantial increase of power dissipation.
In view of the drawbacks associated with the prior art process of producing microstructures with ultra-sub-lithographic features, there is a need for providing a new and improved method that is capable of fabricating microstructures that have ultra-sub-lithographic features and a reduced CD variation preferably of less than 10% (6 σ or range).